1. Field of the Invention
The present invention relates to a flash memory controller, a flash memory system having the controller, and a method of controlling an operation for data exchange between a host system and a flash memory.
2. Description of the Related Art
Recently, a flash memory is widely employed as a semiconductor memory used in a memory system such as a memory card and a silicon disk. The flash memory is one type of non-volatile memories. It is required that the data stored in the flash memory be retained in the flash memory even when electricity is not supplied to the flash memory.
A NAND type flash memory is one type of flash memories often used in the aforementioned memory system. Each of a plurality of memory cells included in a NAND type flash memory can be changed from an erase state where data representing a logical value “1” is stored, to a write state where data representing a logical value “0” is stored, independently from the other memory cells. On the contrary, in a case where at least one of the plurality of memory cells needs to be changed from the write state to the erase state, each memory cell can not be changed independently from the other memory cell. In this case, all of a predetermined number of memory cells which are collectively referred to as a block need to be changed to the erase state. This simultaneous erasing operation is generally referred to as “block erasing”. The block on which the block erasing has been performed is referred to as an erased block.
Due to the above-described characteristic, overwriting of data is not available in the NAND type flash memory. In order to rewrite data stored in a memory cell, block data including new data needs to be written in an erased block first, and then block erasing needs to be performed on the block storing the old data. The rewritten data is stored in a block which is different from the block in which the data before being rewritten was stored. Therefore, the correspondence between a logical block address specified by an address signal supplied from a host system and a physical block address representing the actual block address in the flash memory is dynamically adjusted by a controller each time data is rewritten in the flash memory. For example, the correspondence between the logical block address and the physical block address is described in an address translation table prepared in the controller.
If the correspondence between the logical block addresses and the physical block addresses of all the blocks included in the flash memory is described in an address translation table, the address translation table has to have a large size in accordance with the flash memory having a large data capacity. In order to generate an address translation table having a large size, a large system resource and a long process time are consumed. To solve this problem, Unexamined Japanese Patent Application KOKAI Publication No. 2000-284996 discloses a technique for dividing a memory space in the flash memory into a plurality of zones, and generating an address translation table for the blocks assigned to each zone. Unexamined Japanese Patent Application KOKAI Publication No. 2002-73409 discloses an address translation method for preventing an increase in the memory capacity that is required for using the address translation table, by copying a part of the address translation table stored in the flash memory to a memory space in a RAM. Unexamined Japanese Patent Application KOKAI Publication No. 2003-15946 discloses a memory controller which can perform a series of data writing operations in a flash memory parallely. The memory controller disclosed in this publication is designed to use a plurality of virtual blocks which are formed by virtually combining a plurality of physical blocks belonging to different blocks from each other.
In such a flash memory as disclosed in Unexamined Japanese Patent Application KOKAI Publication No. 2000-284996 having a memory space which is divided into a plurality of zones, existence of a defective block should be taken into consideration for assigning the zones to data areas included in a host system. In other words, it is preferred that the storage capacity of a zone to be assigned to a data area in a predetermined range included in the host system is designed larger than the upper limit of the amount of data to be handled in the data area. At this time, at least one spare block (redundant block) is provided in each zone, such that the ratio of the spare block to all the blocks in the zone is a predetermined value.
However, if many defective blocks exist in one part of a flash memory, the defective blocks concentrate in a zone to which this part is assigned. In a case where the number of defective blocks included in a zone is larger than the number of spare blocks included in this zone, no erased block can be secured and the operation is forced to stop. In a case where many defective blocks concentrate in a specific zone as described above, even though the total number of defective blocks in the flash memory does not exceed the tolerable number for the proper operation, there might be caused a zone that can not store data properly.